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AArch64 W+W+WW+posptevap-[dsb.ish]-[isb]+PteOAPteVA
"CoePteOAPteVA CoePteVAPteVA PosWWPteVAP DSB.ISH ISB CoePPteOA"
variant=precise
Cycle=ISB CoePPteOA CoePteOAPteVA CoePteVAPteVA PosWWPteVAP DSB.ISH
Relax=PteOA PteVA
Safe=Coe [PosWW,DSB.ISH,ISB]
Generator=diy7 (version 7.56+02~dev)
Com=Co Co Co
Orig=CoePteOAPteVA CoePteVAPteVA PosWWPteVAP DSB.ISH ISB CoePPteOA
{
pteval_t 1:X2; pteval_t 0:X2;
int x=0; int y=4;
0:X0=PTE(x); 0:X1=(oa:PA(y));
1:X0=PTE(x); 1:X1=(oa:PA(y), valid:0);
2:X0=PTE(x); 2:X1=(oa:PA(y)); 2:X3=x;
}
P0 | P1 | P2 ;
STR X1,[X0] | STR X1,[X0] | STR X1,[X0] ;
LDR X2,[X0] | LDR X2,[X0] | DSB ISH ;
| | ISB ;
| | MOV W2,#1 ;
| | STR W2,[X3] ;
exists (0:X2=(oa:PA(y), valid:0) /\ 1:X2=(oa:PA(y)) /\ [x]=1 /\ ~fault(P2,x))